1. Field of the Invention
The present invention relates to a driving voltage supply circuit and in particular, to an improved driving voltage supply circuit for a Liquid Crystal Display (LCD).
2. Background of the Related Art
FIG. 1 is a circuit diagram illustrating a related driving voltage supply circuit for an LCD panel. As shown therein, the related driving voltage supply circuit for an LCD panel includes an LCD controller 10, and an input unit 11 that processes 6-bit color signals R, G, and B from the LCD controller 10 in each cycle of the clock signal CLK. The input unit 11 outputs color signal data R[5:0], G[5:0], and B[5:0] to a latch 13. A shift register 12 comprises a plurality of shift registers connected in series, and shifts a shift register start pulse signal SSP in accordance with the clock signal CLK when the shift register start pulse signal SSP is inputted.
A latch unit 13 outputs a signal in accordance with an output enable signal OE when data corresponding to one line is inputted thereto wherein the output data from the input unit 11 is controlled by the output signal from the shift register 12. A digital/analog converter 14 converts the digital color signal data from the latch unit 13 into an analog color signal, and an output buffer 15 buffers the output signal from the digital/analog converter 14 to a predetermined level.
When the color signals R, G, and B and synchronous signals H-SYNC and V-SYNC are inputted, the LCD controller 10 transmits the color signals synchronized with respect to the horizontal synchronous signal H-SYNC and vertical synchronous signal V-SYNC to the input unit 11. The input unit 11 processes the 6-bit color signals from the LCD controller 10 in each cycle of the clock signal CLK. Therefore, the input unit 11 outputs the color signal data R[5:0], G[5:0], and B[5:0] of 18 bits, which were processed in 6 bits with respect to each of the color signals R, G, and B, to the latch unit 13.
In the shift register 12, which includes a plurality of shift registers (not shown), the SSP signal is sequentially shifted in accordance with the clock signal CLK when the SSP signal is applied to a first shift register (not shown). Whenever the SSP signal is outputted through the last shift register (not shown), the color signal from the input unit 11 is inputted into the latch unit 13.
The latch unit 13 holds the color signal from the data input unit 11 in accordance with the output signal from the shift register 12 until the next color signal data is inputted. When the output enable signal OE is inputted, the color signal data from the input unit 11 is transmitted to the digital/analog converter 14. The digital/analog converter 14 converts the digital color signal data from the latch unit 13 into analog color signals, and then transmits the analog color signals to the output buffer 15. The output buffer 15 buffers the analog color signals R, G, and B to a predetermined level. The output voltage from the output buffer 15 is supplied to each pixel of the LCD panel, so that the LCD panel is activated by the color signal voltage.
In the related art, since the operation frequency of the shift register and the input frequency of the clock signal CLK are identical, the power consumption is increased. Accordingly, the circuit may be easily influenced by noise, which causes electromagnetic interference.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.